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시스템해석 과제 - 문제 B-10-19, B-10-20(p.717)

[문제 B-10-19] 그림의 시스템을 고려하자. 시스템의 근궤적을 그려라. 주요 폐루프 극점의 ζ가 0.6이 되도록K값을 결정하라. 그때 모든 폐루프 극점을 결정하라. MATLAB으로 단위계단 응답곡선을 그려라,1. 근궤적 그리기2. K값 구하기THETA `=`cos ^{-1} (0.6)`=`53.13010235s`=`a`+`j(-1.33333333)a 를s(s+1)(s+4)`+`K`=`0식에 대입하면,a _{1} `=`-7.768079286,a _{2} `=`-0.4217388963 을 얻을 수 있다.a _{1} ` -> `K`=`-1765.5##a _{2} -> `K`=`2.0536K값이 양수여야 하므로 K = 2.0536 (안정성)폐루프G(s)`=` {K} over {s(s+1)(s+4)+K} 에서 pole은s(s+1)(s+4)+K`=`0 을 만드는 s.K = 2.0536을 대입하면s = -4.15652s = -0.421739 ?j0.56232s = -0.421739 +j0.562323. 단위계단 응답곡선[MATLAB CODE][문제 B-10-20]그림의 시스템을 고려하자. 주요 폐루프 극점이s`=`-1`±`j1에 위치하도록 PID제어기G _{c} (s)를 설계하는 것이 바람직하다. PID제어기에서 a = 0.5를 선택하고, K와 b의 값을 결정하라. MATLAB으로 근궤적선도를 그려라.1. K와 b구하기s(s ^{2} +1)+K(s+0.5)(s+b)`=`0 의 근이s`=`-1`±`j 이므로 대입하게 되면,(1`-`0.5K`-0.5Kb)`+`j(3-1.5K+Kb)`=`01`-`0.5K`-`0.5Kb`=`0 … ?3`-`1.5K`+`Kb`=`0 … ?2 * ? + ?를 계산하면,K`=`2,`b`=`0를 구할 수 있다.(Ans) K = 2, b = 02. 근궤적그리기 (root locus)

공학/기술| 2019.08.29| 4페이지| 1,000원| 조회(164)

시스템해석, 근궤적, system dynamics

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디지털논리회로실험(Verilog HDL) - 데이터 오류 정정 및 검출, 블랙잭, 계산기 평가A+최고예요

.데이터 오류 검출 및 정정◦ Parity Bit데이터에 패리티 비트를 붙여서 1의 전체 개수가 짝수 혹은 홀수가 되도록 한다.-> 짝수 패리티 사용◦ 1bit 오류 검출 및 정정 시연Key0를 누르면 시작Key1을 누르면 sw중 랜덤으로 1비트 에러가 발생Key2을 누르면 에러 정정Sw[15:0] = {01*************1};◦ Parity bit – 2bit 검사병렬 parity → 해밍 코드 → 병렬 parity + 해밍코드

공학/기술| 2019.08.29| 39페이지| 3,000원| 조회(557)

블랙잭, 디지털논리회로실험, Verilog HDL, 데이터 오류 검출

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디지털논리회로실험(Verilog HDL) - 8-bit Signed Adder/Substractor, Multiplier

1. 관련이론? Adders→ Adds two N-bit binary numbers-2-bit adder: adds two 2-bit numbers, outputs 3-bit result-e.g., 01 + 11 = 100 (1 + 3 = 4)→ Can design using combinational design process of Ch 2, but doesn’t work well for typical N-Why not?1) Why Adders Aren’y Built Using Standard Combinational Design Process⑴ Truth table too big-2-bit adder’s truth table shown :2 ^{(2+2)} `=`16 rows-8-bit adder :2 ^{(8+8)} `=`65,536 rows-16-bit adder :2 ^{(16+16)} `=`~4 billion rows-32-bit adder : ...⑵ Big truth table with numerous 1s/0s yields big logic-Plot shows number of transistors for N-bit adders, using state-of-the-art automated combinational design tool2) Alternative Method to Design an Adder : Imitate Adding bt Hand⑴ Alternative adder design : mimic how people do addition by hand⑵ One column at a time- Compute sum, add carry to next column⑶ Create component for each column- Adds that column’s bits, generates sum and carry bits2) Half-Adder⑴ Half-adder: Adds 2 bits, generates sum and carry⑵ Desite the borrows from columns on left→Use full-substractor component : Wi is borrow by column on right, wo borrow from column on left.? Representing Negative Numbers: Two’s Complement*Negative numbers common-How represent in binary?*Signed-magnitude-Use leftmost bit for sign bit*Better way: Two’s complement-Big advantage: Allows us to perform subtraction using addition.-Thus, only need adder component, no need for separate subtractor component.*Easier method: Just invert all the bits, and add 1.?Two’s Complement Subtractor Built with an Adder*Using two’s complement*So build subtractor using adder by inverting B’s bits, and setting carry in to 1?Adder/Subtractor*Adder/subtractor: control input determines whether add or subtract-Can use 2x1 mux : sub input passes either B or inverted B-Alternatively, can use XOR gates : if sub input is 0, B’s bits pass through; if sub input is 1, XOR inverts B’bits.?Multiplier ? Array style*Can build multiplier that mimics multiplication by hand-Notice thaE2-115 board and test it by using different switch settings.(3) Code변수를 선언하고 A,B, 그리고 cin을 sw[16]으로 하여 8bit adder를 만든다. 결과값은 wireS에 저장한다. hexA,hexB는 A의 실제값이 아닌 7-segment에 띄울 값을 저장한다.key1이 눌리면 sw[15:8]까지의 값을 A가 받고 sw[7:0]까지의 값을 B가 받는다. msb는 부호를 나타내기 때문에 hexA와 hexB에는 msb를 제외한 sw값을 인가받는다. S는 wireS값을 인가받는다. msb가 1이게 되면 signed bit이기 때문에 msb를 제외한 나머지 bit에 two’s complement를 적용시킨 후 더해주어야 한다. sw[16]이 1인 경우는 뺄셈 연산이기 때문에 A ? B를 실행하기 위해 B의 전체 bit을 반전시킨다. 이때는 sw[16]이 cin으로 연산되어 들어가기 때문에 1을 더해줄 필요가 없다. S의 경우에도 msb가 1인 경우에는 two’s complement를 적용한 값을 S에 넣어준다. mark라는 변수는 S가 양수인지 음수인지를 판별하여 양수인 경우 HEX3에는 빈칸을 띄우고 음수인 경우 (-) 표시를 띄우도록 한다.key0가 눌리게 되면 모든 값을 0으로 초기화한다. mark가 0일 때는 HEX3에 아무 값도 띄우지 않는다.각각의 변수는 16진수의 2번째, 1번째, 0번째 자리를 나타내면 display_7seg module을 통해 각각의 HEX값을 인가한다.*display_7seg module각각의 값에 따라 0~F까지 16진수 값을 띄운다.*Full Adder module*Full Adder 8bit moduleFull-Adder module을 8개 붙여놓은 module이다.(4) SimulationA에 3을 인가하고 B에 ?4를 인가한 뒤 더한 값을 띄운다. 즉, 3 + (-4) = -1A에 4값을 인가하고 B에 3값을 인가한 뒤 뺄셈연산을 한다. 즉, 4 ? 3 = 1kar structure, this type if multiplier circuit is usually called an array multiplier. The shaded areas in the circuit correspond to the shaded columns in Figure 2c. In each row of the multiplier AND gates are used to produce the summands, and full adder modules are used to generate the required sums.*조건-SW11-8, SW3-0으로 16진수 숫자 2개 (A와 B) 입력-A는 HEX6에 B는 HEX4에 각각 출력-곱셈의 결과 P는 HEX1-0에 출력(2) Process? Create a new Quartus project which will be used to implement the desired circuit on the Altera DE2-115 board.? Generate the required Verilog file, include it in your project, and compile the circuit.? Use functional simulation to verify that your code is correct? Augment your design to use switchesSW _{11-8} to represent the number A and switchesSW _{3-0} to represent B. The hexadecimal values of A and B are to be displayed on the 7-segment displays HEX6 and HEX4, respectively. The result P = A x B is to be displayed on HEX1 and HEX0.? Assign the pins on the FPGA to connect to the switches and 7plications of digital circuits it is useful to be able to perform some number of multiplications and then produce a summation of the results. For this part of the exercise you are to design a circuit that performs the calculation.S = (A x B) + (C x D)The inputs A, B, C, and D are eight-bit unsigned numbers, and S provides a 16-bit result. Your circuit should also provide a carry-out signalC _{out}.*조건-SW15-8로 A와 C를 입력, SW7-0으로 B와 D를 입력(16진수 입력)-SW16은 A,C와 B,D의 입력을 선택-SW17이 1일 때, 실제 값이 입력됨, 0일 때 값이 입력되지 않음-A,C는 HEX7-6에 표시, B,D는 HEX5-4에 표시, 계산 결과는 HEX3-0에 표시-만약 Carry가 발생하면 LEDG8에 불이 들어오도록 설계(2) Process? Create a new Quartus Ⅱ project which will be used to implement the desired circuit on the Altera DE2 board.? Connect the inputs A and C to switchesSW _{15-8} and connect the inputs B and D to switchesSW _{7-0}. Use switchSW _{16} to select between these two sets of inputs: A, B or C, D. Also, use the switchSW _{17} as a write enable(WE) input. Setting WE to 1 should allow data to be loade.

공학/기술| 2019.08.29| 19페이지| 1,000원| 조회(446)

회로설계, 디지털논리회로실험, Verilog HDL

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디지털논리회로실험(Verilog HDL) - Adders

LAB04 : Adders1.관련이론? Adders→ Adds two N-bit binary numbers-2-bit adder: adds two 2-bit numbers, outputs 3-bit result-e.g., 01 + 11 = 100 (1 + 3 = 4)→ Can design using combinational design process of Ch 2, but doesn’t work well for typical N-Why not?1) Why Adders Aren’y Built Using Standard Combinational Design Process⑴ Truth table too big-2-bit adder’s truth table shown :2 ^{(2+2)} `=`16 rows-8-bit adder :2 ^{(8+8)} `=`65,536 rows-16-bit adder :2 ^{(16+16)} `=`~4 billion rows-32-bit adder : ...⑵ Big truth table with numerous 1s/0s yields big logic-Plot shows number of transistors for N-bit adders, using state-of-the-art automated combinational design tool2) Alternative Method to Design an Adder : Imitate Adding bt Hand⑴ Alternative adder design : mimic how people do addition by hand⑵ One column at a time- Compute sum, add carry to next column⑶ Create component for each column- Adds that column’s bits, generates sum and carry bits2) Half-Adder⑴ Half-adder: Adds 2 bits, generates sum an 2B) Implement as circuit4) Carry-Ripple Adder⑴ Using half-adder and full-adders, we can build adder that adds like we would by hand⑵ Called a carry-ripple aadder-4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output-Can easily build any size adder⑶ Using full-adder instead of half-adder for first bit, we can include a “carry in” bit in the addition-Useful later when we connect smaller adders to form bigger adders5) Carry-Ripple Adder’s Behavior6) Cascading Adders2.1 part3 : 4-bit Ripple Carry Adder? 실험목적: 4-bit Ripple Carrry Adder를 구현한다.? 실험내용(1) SummaryFigure 2a shows a circuit for a full adder, which has the Input a, b, andc _{i}, and produces the output s andc _{o}. parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sumc _{o} s`=`a`+`b`+`c _{i}. Figure 2d shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually caⅡ project for the adder circuit. Write a Verilog module for the full adder subcircuit and write a top-level Verilog module that instantiates four instances of this full adder.2. Use switchesSW _{7-4} andSW _{3-0} to represent the inputs A and B, respectively. UseSW _{8} for the carry-incin of the adder. Connect the SW switches to their corresponding red lights LEDR, and connect the outputs of the adder,c_{ out} and S, to the green lights LEDG.3. Include the necessary pin assignments for the DE2-series board, compile the circuit, and download it into the FPGA chip.4. Test your circuit by trying different values for numbers A, B, andcin.(3) Code : input a(4bit),b(4-bit),cin을 받아서 Full-adder 연산을 통해 output s(5-bit)를 계산한다.(4) Simlulation여기서 co은 output s의 가장 첫 번째 bit을 의미한다. ex) a + b + ci = 10001 -> co = 1 s = 0001로 나온다.(5) Flow-chart2.2 partⅣ : 1-Digit BCD Adder? 실험목적 : 1-Digit BCD Adder를 구현할 수 있다.? 실험내용(1) SummaryIn part Ⅱ we discussed the conversion of binary numbers into decimal digits. Itation. As an example, the decimal value 59 is encoded in BCD form as 0101 1001You are to design a circuit that adds two BCD digits. The inputs to the circuit are BCD numbers A and B, plus a carry-in, cin. The output should be a two-digit BCD sumS _{1} S _{0}. Note that the largest sum that needs to be handled by this circuit isS _{1} S _{0} = 9 + 9 + 1 = 19. Perform the steps given below(2) Process1. Create a new Quartus Ⅱ project for your BCD adder. You should use the four-bit adder circuit from part Ⅲ to produce a four-bit sum and carry-out for the operation A + B. A circuit that converts this five-bit result, which has the maximum value 19, into two BCD digitsS _{1} S _{0} can be designed in a very similar way as the binary-to-decimal converter from part Ⅱ. Write your Verilog code using simple assign statements to specify the required logic functions-do not use other types of Verilog statements such as if-else or case statements for this part of the exercise.2. Use switchesSW _{7-4ation A + B to the green lights LEDG. Display the BCD values of A and B on the 7-segment displays HEX6 and HEX4, and display the resultS _{1} S _{0} on HEX1 and HEX0.3. Since your circuit handles only BCD digits, check for the cases when the input A or B is greater than nine. If this occurs, indicate an error by turning in the green light LEDG{}_{8}.4. Include the necessary pin assignments for the DE2-series board, compile the circuit, and download it into FPGA chip.5. Test your circuit by trying different values for numbers A,B, and cin.(3) Codecomparator_3bit 계산을 통해 A,B 각각이 10 이상인지 검사한다.A,B, cin을 계산하여 전체 sum 인 s를 계산한 후, part2에서 했던 7-segment display를 적용한다.circuitB 연산은 z = 1이면 HEX에 1을 띄우고 0인 경우 HEX에 0을 띄우는 module이다.circuitA는 z =1일 때 일의자리 숫자를 연산한다.mux는 z = 1일 때, M을 V로 z = 0일 때 M을 U로 설정한다.FA 는 full-adder연산으로 input a,b,cin을 받아 output s,co을 만들어 낸다. 마지막 연산에서 co은 s[4]가 된다.comparator는 input V가 10이상이 되면 z를 1로 만들고 아닌 경우 z=0이 된다.위 모듈을 sw의 input에 따라 HEX(7-segment) display를 한다.(4) SimlulationA 가 9rt

공학/기술| 2019.08.29| 12페이지| 1,000원| 조회(300)

실험레포트, 디지털논리회로실험, Verilog HDL

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디지털논리회로실험(Verilog HDL) - Numbers and Displays

LAB03: Numbers and Displays1. 관련이론? Multiple-Output Circuits- Many circuits have more than one output- Can give each a separate circuit, or can share gates- Ex: BCD to 7-Segment Converter? Decoder : Popular combinational logic building block, in addition to logic gates- Converts input binary number to one high output# 2-input decoder : four possible input binary numbers- So has four outputs, one for each possible input binary number# Internal Design- AND gate for each output to detect input combination# Decoder with enable e- Outputs all 0 if e=0- Regular behavior if e=1# n-input decoder:2 ^{n} outputs# Example : New Year’s Eve Countdown Display- Microprocessor counts from 59 down to 0 in binary on 6-bit output- Want illuminate one of 60 lights for each binary number- Use 6x64 decoder (4 outputs unused)? Mux : Another populer combinational building block-Routes one of its N data inputs to its one output, based on binary value of select inputs-N bits ->log _{2} N selects-Like a rail yard switch-Mux Internal Design-Mux Commonly Together ? N-bit MuxEx) Two 4-bit inputs, A(a3,a2,a1,a0), and B(b3,b2,b1,b0)-> 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B2. 실험2.1 partⅠ: 7-Segment Display of Decimal Inputs? 실험목적 : binary to decimal displaying 7-segment? 실험내용⑴ SummaryWe wish to display on the 7-segment displaysHEX3 toHEX0 the values set by the switchesSW _{15-0}. Let the values denoted bySW _{15-12},SW _{11-8},SW _{7-4},SW _{3-0} be displayed onHEX3,HEX2,HEX1, andHEX0, respectively. Your Circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don’t cares.⑵ Process1) Create a new project which will be used to implement the desired circuit on the Altera DE2-series board. The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays. You should use only simple Verilog assign statements in your code and specify each logic function as a Boolean expression.2) Write a Verilog file that provides the necessary functionality. Include this file in your project and assign the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User Manual for the DE2-series board. The procedure for making pin assignments is described in the tutorial QuartusⅡ Introduction using Verilog Design, which is available on the DE2-Series System CD and in the University Program section of Altera’s web site.3) Compile the project and download the compiled circuit into the FPGA chip.4) Test the functionality of your design by toggling the switches and observing the displays.⑶ Code⑷ Simulation(5) Flow-chart2.2 partⅡ: 4-bit Binary to 2-digit Decimal Converter? 실험목적 :4-bit Binary 숫자를 2-digit Decimal 숫자로 바꿀 수 있다.? 실험내용⑴ SummaryYou are to design a circuit that converts a four-bit binary numberV`=`v3v2v1v0 into its two-digit decimal equivalentD`=`d1d0. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value ofV is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit by creating a Verilog module which includes the comparator, multiplexers, and circuit A (do not include circuit B or the 7-segment decoder at this point). Your Verilog module should have the four-bit input V, the four-bit output M and the output z. The intent of this exercise is to use simple Verilog assign statements to specify the required logic functions using Boolean expressions. Your Verilog code should not include any if-else,case,or similar statements.⑵ Process1) Make a Quartus Ⅱ project for your Verilog module2) Compile the circuit and use functional simulation to verify the correct operation your comparator, multiplexers, and circuit A.3) Augment your Verilog code to include circuit B in Figure 1 as well as the 7-segment decoder. Change the inputs and outputs of your code to use switchesSW _{3-0} on the DE2-series board to represent the binary number V, and the displaysHEX1 andHEX0 to show the values of decimal digitsd _{1} andd _{0}. Make sure to include in your project the required pin assignments for the DE2-series board.4) Recompile the project, and then download the circuit into the FPGA chip.5) Test your circuit by trying all possible values of V and observing the output displays.⑶ Code⑷ Simulation(5) Flow-chart

공학/기술| 2019.08.29| 11페이지| 1,000원| 조회(220)

실험레포트, 디지털논리회로실험, Verilog HDL

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