[물리전자2] 과제5 내용 요약 Load line부터 (6단원)

소개

Solid State Electronic Devices By Ben Streetman & Sanjay Banerjee Seventh Edition (2016)
책을 기반으로 한 광운대학교 물리전자2 수업의 5번째 과제입니다.

Ch.6 FET에 대해 Load line부터의 내용을 담았습니다.
해당 과제물들과 함께 A+를 받은 자료입니다.

목차

1 - a. For figure 6-2, significance and purpose of load line
1 - b. For figure 6-2, purpose of VG in 6-2(a), 6-2(b)?

2. For figure 6-3, how JFET can be controlled in terms of biasing among S, G & D

3 - a. For figure 6-4, what is pinch-off
3 – b. For figure 6-4, how about the current ID beyond pinch-off if VD increases?

4. For figure 6-5, if you increase VG, what is the result?

5. equation for ID before the pinch-off

6. equation for ID after the pinch-off

7. For figure 6-7, explain the operational principle of MEtal-Semiconductor junction FET. (how and why it can be turned on&off.

8. For figure 6-8, show how the HEMT can be constructed. (how mobility and carrier concentration can be increased)

9 - a. For figure 6-10, Explain the on & off for n-type, p-type MOSFET regarding VG.
9 – b. For figure 6-10, Explain the on & off states the enhancement type n-channel MOSFET in terms of the band diagram along channel. (band diagram along channel with VG)

10. For figure 6-11, Explain 3 different operating conditions in terms of ID. (show how the ID responds to each condition)

11. For figure 6-12, Explain 4 different band diagrams for the ideal MOS structure in regard to the degree of P-type semiconductor as discussed in the class. In other words, explain the hole carrier concentrations at the metal and semiconductor interface.

12. For figure 6-13, explain Equ. 6.15 in terms of Fig. 6.-13. What does the Equ. 6.15 indicate?

13 - a. For figure 6-15, What is the maximum value of the depletion width under the stronger inversion? Write the regarding equation from the chapter.
13 – b. For figure 6-15, What is the ideal threshold voltage? Write the regarding equation from the chapter

14 - a. For figure 6-16, What is the total capacitance? Write the regarding equation from the chapter.
14 - b. For figure 6-16, What is the insulator capacitance Ci? Write the regarding equation from the chapter.
14 - c. For figure 6-16, What is the depletion (layer) capacitance Cd? Write the regarding equation from the chapter.

15. For figure 6-18 & 19, what does the Equ. 6.37 indicate? In other words, why both terms are negative.

16 – a. For figure 6-20, Explain the VT(V) in terms of doping level for P- & N-type of semiconductors. In other words, explain the sign of VT for P & N type of semiconductors.
16 – b. For figure 6-20, Explain what does the negative VT means for n-channel?

17. Solve Example 6-1 for Na = 5 x 1017cm-3& Qi = 4 x 1015 qC/cm2 for n-channel MOS transistor. Find
Ci and Cmin on the C-V characteristics, and find Wm, VFB, and VT.

18. Identification of source of data

본문내용

1 - a. For figure 6-2, significance and purpose of load line
To predict the current values output in response to externally applied voltage, a load line is necessary. While it is possible to graphically represent the internal values of a transistor, such as vD and iD, through experimentation, expressing them in mathematical equations can be challenging. In this case, the intersection point on the graph of the equation E = iDR + vD and the transistor's I-V characteristic, when both are plotted on the same graph, becomes the steady-state value of the current and voltage.

1 - b. For figure 6-2, purpose of VG in 6-2(a), 6-2(b)?
In Fig. 6-2(b), it can be observed that iD and vD vary with VG. As VG increases, the steady-state value of the current increases while the voltage decreases. Conversely, as VG decreases, the current decreases, and the voltage increases. In other words, increasing VG leads to a higher current, turning on the transistor, while decreasing VG results in reduced current, turning it off.

참고자료

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