Design Timer & AHB Arbiter (임베디드 시스템) AMBA 구현

소개

Design Timer & AHB Arbiter를 구현하는 프로젝트 이다. AMBA의 구현이라고도 할 수 있는데 Timer와 AHB Arbiter를 구현하고 이를 검증하는 과정이다. 자세한 설명과 함께 소스코드와 결과 그림등이 함께 실려져 있다. 비슷한 프로젝트나 과제를 하는 분에게 큰 도움이 될 것이다.

목차

I . Timer
I-a . Subtracts of Timer
I-b . Design of Timer
i. Block diagram
ii. Signal of Timer
iii. Basic actions of Timer
I-c . Method of test
I-d . Simulation and Timing diagram
I-e . Conclusion


II. AHB ARBITER
II-a . Subtracts of Arbiter
II-b . Design of Aribiter
i. Specification
ii. Arbiter Processing Procedure
iii. Round Robin
iv. HGRANT & HMASTER
II-c . Method of test
II-d . Simulation and Timing diagram


III. APPENDIX
III-a . Timer Verilog Code
III-b . Arbiter Verilog Code

본문내용

I. Timer
a. Subtracts of Timer
Every watch in your home has it own period. This timer is one of those clocks. It has steady flow time. Clock signal make that flow like weights of the watch. We make 32-bit Timer. When we insert the wanted value that occur interrupt and make enable timer by control signal, we make the timer that makes interrupt in that time. Timer in preliminary SPEC has set of 2 timers. But this timer works by it-self. Like behind block diagram timer has register and counter and some logic gate.

b. Design of Timer
i. Block diagram

< Figure Ⅰ-1. Simple Timer block diagram >
The block diagram of timer is like Figure Ⅰ-1. It is consis of one counter and one data register for interrupt, comparator. And interrupt signal is generated by combinational circuit which inputs are interrupt control bit and comparator output signal.

ii. Signals of Timer

< Figure Ⅰ-2. Signal of Timer and Timer verilog code variable >
The signals of timer are like Figure Ⅰ-2. The one of main signals are TMR32CON which indicate timer enable or disable and interrupt is enabled or disabled. TMR32CNT indicate the current time.

참고자료

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