leejhuek 스토어

leejhuek

개인인증

팔로워1 팔로우

소개

등록된 소개글이 없습니다.

전문분야 등록된 전문분야가 없습니다.

판매자 정보

학교정보

입력된 정보가 없습니다.

직장정보

입력된 정보가 없습니다.

자격증

입력된 정보가 없습니다.

판매지수

판매중 자료수

37개
전체 판매량

80개
최근 3개월 판매량

0개
자료후기 점수

-
자료문의 응답률

-

전체자료 37개

판매자 표지

Semiconductor Device and Design - 13~14__

Semiconductor Device and Design – 13~14 KwangWoon UniversityContents 1. Full and Semi Custom 2. FPLD Design1. Custom1. Full custom Full Custom Design ▶ How designers design all circuits without using standardized Cell Library1. Full custom Full Custom Design ▶ Advantage : Low Chip price ( it can achieve excellent performance and reduce arera even though production cost is expensive ▶ Disadvantage : Longer design periods, higher complexity and risk1. Semi custom Semi Custom Design (=Quick Design) ▶ Design method using Standard Cell and memory generator(Used primarily for digital design) ▶ Advantage : Simplicity, Popularity ▶ Disadvantage : Cell Type Performance Limited : Non-Efficiency of Design Area1. Semi custom 1) Gate array ▶ Basic logic gate such as NAND and NOR, or metal Routing, which regularly array fully functional devices such as stand logic devices, is stored in the wafer with a chip that has completed the previous process1. Semi custom 1) Gate array ▶ Advantage : Since only metal mask Process is required, Turn around time is half. Appropriate to implement a digital system. ▶ Disadvantage : The die cost is higher because Si area is in-efficient compared to Standard Cell or Full-Custom. Power consumption is high and Switching speed is low.1. Semi custom 2) Standard Cell ▶ Store Standard Cell, implemented as a Full- Cusomized Layout Design, in Cell library for the automation of Layout Design, to minimize wiring with the necessary Blocks.1. Semi custom 2) Standard Cell ▶ Advantage : Si area is used more efficiently than Gate Array method and Chip Speed is improved ▶ Disadvantage : Design cost increase(But cost decrease when mass-produced), Development Speed is Low.2. FPLD FPLD ▶ From the perspective of semiconductor manufacturers, it falls into the category of general purpose IC because it is mass-produced and used for general purposes. From a user perspective, it falls into the ASIC category because it can be programmed and used to meet user needs.2. FPLD FPLD ▶ Basic structure : Input Buffer - AND array - OR array - Output Buffer2. FPLD FPLD ▶ Advantage : Programming time is short. No NRE cost. The programmed circuit can be tested immediately. ▶ Disa dvantage : The use of SI area is inefficient. Individual unit prices are high. have a limited number of gates lack integration and flexibility2. FPLD FPLD Device PROM PAL PLA price medium medium High Speed High medium low Progamming OR AND OR,AND Ease of use Appropriate Appropriate Appropriate2. FPLD Full Custom, Semi Custom, PLDReference [1] Basic Electronics for Scientists and Engineers : Dennis L. Eggleston [2] https://www.electronics-tutorial.net/Programmable-Logic-Device-Architectures/Programmable-Logic-Devices/Programmable-Array-Logic-PAL/ [3] http://www1.pldworld.com/html/technote/pld/asicoverview.htm [4] https://www.quora.com/What-is-difference-between-semi-custom-design-and-full-custom-designThank you{nameOfApplication=Show}

공학/기술| 2023.06.22| 17페이지| 2,000원| 조회(114)

Design, Semi Conductor, FPLD

미리보기

닫기
판매자 표지

Semiconductor Device and Design - 8_

Semiconductor Device and Design - 7 KwangWoon UniversityContents 1. CMOS process design rules 2. The method of implementing the half-adder 3. Layout of the full-adder cell 4. parasitic circuit1. Cmos process design rules ■ Cmos design rules : The physical mask layout of any circuit to be manufacture using a particular process. It must conform to a set of geometric constraints or rules, which are generally called layout design rules. The main objective of design rules is to achieve, a high overall yield and reliability while using the smallest possible silicon area. - Minimum allowable line widths such as metal and poly- si interconnects1. Cmos process design rules - Minimum feature dimensions -Minimum allowable separations between two such features. : Design rules which determin the separation between the Nmos and the Pmos transistor of the CMOS inveter1. Cmos process design rules - Minimum feature dimensions -Minimum allowable separations between two such features. : Design rules which determin the separation between the Nmos and the Pmos transistor of the CMOS inveter■ Micron rules : layout constraints such as minimum feature sizes and minimum allowable feature separations are stated in terms of absolute dimensions in micrometers. ■ Lambda rules : specify the layout constraints in terms of a single parameter and allow linear, proportional scaling of all geometrical constraints. 1. Cmos process design rules The design rules are usually described in two ways :2. Method of implementing Half-adder ■ Exclusive or gate2. Method of implementing Half-adder ■ And gate2. Method of implementing Half-adder ■ Half-Adder logical circuit3. Layout of the full-adder ■ full-adder logic symbol and truth table3. Layout of the full-adder ■ full-adder schematic3. Layout of the full-adder ■ full-adder layout4. parasitic circuit ■ parasitic resistance The reason for parasitic resistance : This is because the process is not perfect and the Gate is raised above the Source, Drain.4. parasitic circuit ■ parasitic resistance Method of reducing parasitic resistance : Find out exactly the length of the channel, which is the passage through which the current flows, and raise it only by the length of the gate. : The method of measuring channel Length4. parasitic circuit ■ parasitic conductance Parasitic capacitance , or stray capacitance is an unavoidable and usually unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. Ciss is the input capacity . Gate – Source-to-Source Cgs and Gate-to-Drain Cgd combined , the total MOSFET capacity viewed from the input side . Cos is the output capacity . Drain – Capacity Between Sources Cds and Gate – Combined capacity Cgs between Drain , the total capacity on the output side . Crss is the gate – drain-to-drain capacity Cgd itself and is called the return capacity or inverted capacity . As the graph shows , larger VDSes tend to result in smaller capacity .4. parasitic circuit ■ parasitic conductance Method of reducing parasitic conductance : 1. Use higher metals for the net in which parasitic capacitance is important. 2. Increase the spacing of all the nets from the net which is critical (for which parasitic capacitance is important). 3. Put some other reference signal (with which parasitic capacitance is not so important) in between the nets for which lower parasitic capacitance required. This is shielding. 4. Avoid too much parallel routing of metals.Reference [1] Basic Electronics for Scientists and Engineers : Dennis L. Eggleston [2] https://www.elprocus.com/half-adder-and-full-adder/ [3]http://blog.naver.com/PostView.nhn?blogId=jis2312 logNo=221295181241 parentCategoryNo= categoryNo=14 viewDate= isShowPopularPosts=true from=search[4] https://www.researchgate.net/figure/Bipolar-process-overview-of-device-type-B-with-deposited-and-wet-etched-silicon-nitride_fig2_226216054 [4] https://techweb.rohm.co.kr/knowledge/si/s-si/03-s-si/4873Thank you{nameOfApplication=Show}

공학/기술| 2023.06.22| 18페이지| 2,000원| 조회(109)

설계, CMOS, Semi Conductor

미리보기

닫기
판매자 표지

Semiconductor Device and Design - 3,

■ Germanuim was used as the original semiconductor material. Later, silicon became the material of choice for Ics.Bandgap 〮Si(1.12eV), Ge(0.66eV)Operating temperature 〮Si can be operated up to ~150℃ while Ge can be operated up to ~100 ℃.

공학/기술| 2023.06.22| 15페이지| 2,000원| 조회(82)

실험설계, 실험레포트, Semi Conductor

미리보기

닫기
판매자 표지

Semiconductor Device and Design - 2,

■ Germanuim was used as the original semiconductor material. Later, silicon became the material of choice for Ics.- Bandgap 〮Si(1.12eV), Ge(0.66eV)- Operating temperature 〮Si can be operated up to ~150℃ while Ge can be operated up to ~100 ℃.

공학/기술| 2023.06.22| 19페이지| 2,000원| 조회(91)

실험보고서, 실험설계, Semi Conductor

미리보기

닫기
판매자 표지

Semiconductor Device and Design - 1,

ConductorsConductors are highly conductive materials that are easily electrically charged. ** Conductivity : Electrical conductivity is the measure of the amount of electrical current a material can carry or it's ability to carry a current.

공학/기술| 2023.06.22| 19페이지| 2,000원| 조회(107)

semiconductor, Inductor, resistance

미리보기

닫기